The present invention generally relates to a magnetic recording/reproducing apparatus, and particularly relates to a digital audio tape recorder (hereinafter referred to as "DAT") of the rotary head type.
In a DAT of the rotary head type, in order to perform high-speed random selection of tunes (review of tunes) at a speed of ten times or hundred times as high as a normal reproducing speed, it is necessary to correctly read a signal indicating start of a tune, a signal for performing time indication, a signal representing tune number, etc., which are recorded on a track with the same recording density as a music PCM signal.
If a tape is made to run at a high speed which is different from the speed in normal recording/reproducing, the scanning locus of a head intersects a signal track on the tape a plurality of times so that the relative speed of the head and tape varies under the condition in which the rotating speed of a cylinder is constant.
In a DAT, on the other hand, a data strobe circuit is employed as a circuit for reproducing a digital signal from a signal reproduced by a head. In this circuit, the input transmission rate has a margin of about .+-.10% against speed deviations and jitters in the tape running system, and the speed of the tape relative to the head varies in high speed rotation of the tape, so that if the input signal transmission rate comes out the range of the margin of about .+-.10%, there occurs such a disadvantage that the data reproduction becomes impossible, that is, random access becomes impossible.
In a DAT, accordingly, it is impossible to make the cylinder rotation speed high speed rotation of the tape the same as that in normal recording/reproducing operation, and it is indispensably necessary to perform follow-up control in accordance with the tape running speed so as to maintain the relative speed between the head and tape constant or to maintain the jitter in the data strobe circuit within an allowable range. As a control apparatus to make the cylinder rotation speed vary in accordance with the tape running speed so as to control the relative speed between the head and tape to be constant, there are those disclosed, for example, in Japanese Patent Unexamined Publication Nos. 61-214164 and 61-110359. In those control apparatuses, the cylinder rotation speed is controlled so that the reproduction clock frequency obtained as a frequency synchronized with a reproduction signal in a data strobe circuit is set at a predeterminedly fixed frequency.
In a recording/reproducing apparatus, such as a digital audio tape recorder, for recording/reproducing information by a rotary drum, it is necessary to control the rotation of each of a capstan shaft, a reel and the rotary drum.
In the past, circuits as shown in FIGS. 13 and 14 have been employed as circuits for controlling the rotation of the capstan shaft and the reel. In the following, the circuits are described.
FIG. 13 shows a capstan servo circuit, in which the reference numeral 1 designates an FG frequency divider for dividing the frequency of an output signal obtained from an FG of a capstan motor. The FG frequency divider has a frequency division step capable of obtaining a suitable tape speed by changing the frequency-division rate of the signal when the capstan shaft is rotated in a variable speed mode, and capable of being through in the normal recording/reproducing period. The reference numeral 2 designates a capstan speed comparator for counting the period of the FG signal from the FG frequency divider 1 by clock pulses CK.sub.1 to thereby detect the deviation between the FG signal period and a reference period as a digital speed error. The reference numeral 3 designates a pulse-width modulator for pulse-width-modulating the digital speed error obtained by the capstan speed comparator 2. The reference numeral 4 designates a low-pass filter for selecting low-band pulses from the pulse signal given by the pulse-width modulator 3 to pass the low-band pulses. Thus, an analog error voltage is generated from the low-pass filter. The aforementioned parts constitute a capstan servo speed control system.
The reference numeral 5 designates a PG frequency divider for dividing the frequency of the FG frequency-divider output obtained by the FG frequency divider 1 so as to make the frequency equal to the frequency of a phase reference signal. The reference numeral 6 designates a capstan phase comparator for counting, on the basis of clock pulses CK.sub.2, the phase deviation between the PG frequency divider output obtained by the PG frequency divider 5 and a phase reference signal to thereby detect the phase deviation as a digital phase deviation. The reference numeral 7 designates a pulse-width modulator for pulse-width-modulating the digital phase error obtained by the capstan phase comparator 6. The reference numeral 8 designates a low-pass filter which is arranged to allow only low-band pulses of the pulse signal given by the pulse-width modulator 7 to pass therethrough as an analog error voltage. The aforementioned parts constitute a capstan servo phase control system.
The reference numeral 9 designates an adder for adding the speed error voltage and the phase error voltage of the capstan motor at a suitable gain rate.
The operation of the circuit will be described with reference to the aforementioned construction of the circuit. The FG signal from the capstan motor is frequency-divided by the FG frequency divider 1. Then, the resultant signal is outputted as a digital speed error from the capstan speed comparator 2. The output from the capstan speed comparator 2 is converted into an analog error voltage through the pulse-with modulator 3 and the low-pass filter 4, and the analog error voltage is in turn applied to the adder 9.
On the other hand, the signal frequency-divided by the FG frequency divider 1 is further frequency-divided by the PG frequency divider 5 so as to be made equal to the frequency of a phase reference signal, and then, the resultant signal is outputted as a digital phase error from the capstan phase comparator 6. The output from the capstan phase comparator 6 is applied to the adder 9 as an analog error voltage through the pulse-width modulator 7 and the low-pass filter 8.
Accordingly, the adder 9 operates to add the speed error voltage and the phase error voltage of the capstan motor to each other at a suitable gain rate and supply the resultant voltage to a capstan motor driver circuit (not shown) to thereby control the capstan shaft to keep its rotation speed constant.
FIG. 14 is a circuit diagram in the case where tape speed is required to be kept substantially constant as in the search time in a digital audio tape recorder. In the circuit, a servo is applied to a reel motor to keep the sum of the respective periods of a take-up reel FG signal and a feed reel FG signal constant. The reference numerals 10 and 11 designate edge detectors for detecting leading and trailing edges of the FG signals from take-up and feed reels, respectively. The reference numeral 12 designates a switching circuit for switching the respective edge-detection signals to count, by a next-stage counter, one period of the take-up reel FG signal and one period of the feed reel FG on the basis of the edge-detection signals obtained by the edge detectors 10 and 11, alternatively. The reference numeral 13 designates a reel speed comparator which counts the one period of the take-up reel FG signal on the basis of clock pulse CK.sub.3 and then counts the one period of the feed reel FG signal on the basis of the clock pulses CK.sub.3 following the counting of the take-up reel FG signal. The reference numeral 14 designates a pulse-width modulator for pulse-width-modulating a digital speed error given by the reel speed comparator 13. The reference numeral 15 designates a low-pass filter which operates to allow low-band pulses of the pulse signal given from the pulse-width modulator 14 to pass therethrough so as to output them as an analog error voltage. In short, upon completion of counting one period of the take-up reel FG signal and one period of the feed reel FG signal by the counter of the reel speed comparator 13, the count value at this point in time becomes an error voltage representing a digital speed error
The operation of the circuit will be described with reference to the aforementioned construction of the circuit. As shown in FIG. 15, when the measurement of the sum of periods is started, the switching circuit 12 outputs a high-level signal, for example, during one period of the take-up reel FG signal, that is, during one period in which two edge pulses are output. Then, when an edge pulse of the feed reel FG signal is supplied to the switching circuit, the switching circuit outputs ,a high-level signal again during one period of the feed reel FG signal. The output signal from the switching circuit 12 is applied to a counting terminal of the counter of the reel speed comparator 13, so that clock pulses are counted while the terminal is in a high level. When the one period of the take-up reel FG signal and the one period of the feed reel FG signal have been measured by the counter, the count value of the counter is latched and then converted into a pulse signal which is in turn output as an analog error voltage through the low-pass filter 14. The analog error voltage is supplied to a reel motor driver (not shown).
Once latched, the count data of the reel speed comparator 13 is cleared or reset so as to perform the next period sum measurement mode.
In the afore-mentioned high speed access control, it is impossible to rapidly increase the tape speed, that is the rotation speed of a reel motor for driving a reel mount, simultaneously with the start of access. This is because, if the tape speed is increased rapidly the aforementioned cylinder follow-up servo may unlock because of delay in rotation speed follow-up due to the inertia of the cylinder. Accordingly, it is necessary to gradually or gently increase the speed of the tape, that is, the gradually increase the rotation speed of the reel motor, to achieve a high rotation speed.
In the foregoing prior art, the gradual increase in the high speed rotation tape is not taken into consideration, and therefore has had a problem when rapidly increasing the speed of rotation of the reel motor, since this rapid increase causes, the follow-up control of the cylinder rotation speed to very such that the relative speed between the head and tape deviates to such a degree that data reproduction is impossible.
In the aforementioned servo circuit, it is necessary to control the capstan motor and the reel motor by servo circuits provided separately. Accordingly, there arises a problem in that the circuit is complicated in construction, which increases the cost and space.